1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor integrated circuit with a stack package structure.
2. Description of the Related Art
In general, packaging technologies for semiconductor integrated circuits have continuously been developed to satisfy the demand toward reducing size and mounting reliability. Recently, as reduction in size and high performance are demanded in electric and electronic products, various techniques for stack packages have been developed.
The term “stack” that is referred to in the semiconductor industry means to vertically pile at least two semiconductor chips or semiconductor packages. For example, in the case of a semiconductor memory device, by using a stack package, a product with memory capacity at least two times greater than that obtainable without a stack package may be realized. Since the stack package provides advantages in terms of not only memory capacity but also mounting density and mounting area utilization efficiency, research and development for the stack package have been accelerated.
Generally, a stack package may be fabricated through a method in which individual semiconductor chips are stacked and then the stacked semiconductor chips are packaged at once or a method in which individually packaged semiconductor chips are stacked. The individual semiconductor chips of the stack package are electrically connected through metal wires or through-chip vias. Specifically, a stack package using through-chip vias has a structure in which through-chip vias are formed in the individual semiconductor chip such that physical and electrical connections between the semiconductor chips are formed by the through-chip vias.
FIG. 1 is a perspective view for illustrating a semiconductor integrated circuit in which electrical connections are formed through through-chip vias.
Referring to FIG. 1, a semiconductor integrated circuit 100 includes a first semiconductor chip 101 which is electrically connected with an external controller (not shown), second to fifth semiconductor chips 103, 105, 107 and 109 that are vertically stacked on the first semiconductor chip 101, and a plurality of first to fourth through-chip vias 113, 115, 117 and 119 that vertically pass through the second to fifth semiconductor chips 103, 105, 107 and 109.
The first semiconductor chip 101 is configured to control the second to fifth semiconductor chips 103, 105, 107 and 109 through the first to fourth through-chip vias 113, 115, 117 and 119 based on various signals and power provided from the external controller, and is generally referred to as a master chip.
The second to fifth semiconductor chips 103, 105, 107 and 109 are semiconductor chips for performing given operations under the control of the first semiconductor chip 101, and are generally referred to as slave chips.
The first to fourth through-chip vias 113, 115, 117 and 119 are formed of a metal with high conductivity, and are generally referred to as through-silicon vias (TSVs).
According to the semiconductor integrated circuit 100, as the various signals and power are interfaced through the first to fourth through-chip vias 113, 115, 117 and 119, advantages are provided in that signal delay and current consumption may be decreased and operation performance may be improved due to improved I/O bandwidth.
However, the semiconductor integrated circuit 100 configured as mentioned above has the following concerns.
While it is illustrated in FIG. 1 that the respective semiconductor chips 103, 105, 107 and 109 have two through-chip vias 113, 115, 117 and 119, each of the semiconductor chips 103, 105, 107 and 109 actually has several hundreds to several thousands of through-chip vias therein. Since the through-chip vias vertically pass through the semiconductor chips, the more the numbers of the through-chip vias increase, the more the areas occupied by the through-chip vias increase. Thus, the areas of the semiconductor chips increase as well. In order to reduce the areas, the numbers of the through-chip vias should be decreased, so that limitations exist in improving bandwidth.
As mentioned above, the various signals and power are interfaced between the stacked semiconductor chips. In particular, in the case where multi-bits data is interfaced, operation performance may be adversely influenced by a skew that inevitably occurs due to a characteristic of interfacing.